(1) Field of the Invention
This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically to an improved process for chemical/mechanical planarization (CMP) of an insulating layer deposited over topography on a semiconductor substrate.
(2) Description of Related Art
Chemical/mechanical polishing (CMP) has been developed for providing planar topographies on surfaces deposited on semiconductor substrates. For example, rough topography results when metal conductor lines are formed over a substrate containing device circuitry. The metal conductor lines serve to interconnect discrete devices, and thus form integrated circuits. The metal conductor lines are further insulated from the next interconnection level by thin layers of insulating material and holes formed through the insulating layers provide electrical access between successive conductive interconnection layers. In such wiring processes, it is desirable that the insulating layers have a smooth surface topography, since it is difficult to lithographically image and pattern layers applied to rough surfaces.
Briefly, the CMP processes involve holding and rotating a thin, flat substrate of the semiconductor material against a wetted polishing surface under controlled chemical, pressure, and temperature conditions. A chemical slurry containing a polishing agent, such as alumina or silica, is used as the abrasive material. Additionally, the chemical slurry contains selected chemicals which etch various surfaces of the substrate during processing. The combination of mechanical and chemical removal of material during polishing results in superior planarization of the polished surface.
Alternate planarization processes have, also, been developed. U.S. Pat. No. 5,051,602 entitled "Method of Manufacturing a Semiconductor Device Having a Planarized Construction" granted May 14, 1991 to Paulus A. Van Der Plas et al describes a method of planarization of a first layer deposited over topography, in which the first layer is preplanarized by providing a photoresist mask over depressed areas and etching the unprotected first layer to form a partially planarized surface of the first layer. Next a second planarizing layer is applied, followed by a blanket etchback step which etches the second planarizing layer and the first layer at substantially the same rate. The second planarizing layer is completely removed and the first layer is etched producing a planar surface.
U.S. Pat. No. 4,954,459 entitled "Method of Planarization Of Topologies In Integrated Circuit Structures" granted Sep. 4, 1990 to Steven C. Avanzino et al describes a method of planarization of an oxide layer deposited over topography, in which a patterned photoresist mask is applied with openings in registry with raised portions of the oxide layer. The raised oxide portions are etched down to approximately the same height as low portions of the oxide layer; then the photoresist mask is removed; and chemical/mechanical polishing (CMP) is used to produce a planarized surface.
U.S. Pat. No. 5,350,486 entitled "Semiconductor Planarization Process" granted Sep. 27, 1994 to Kuei-Wu Huang describes a method for planarizing an oxide layer deposited over topography, in which a layer of spin-on glass is first formed over the oxide layer, followed by formation of a patterned photoresist mask with openings in registry with raised portions of the spin-on glass. Next, the regions of the spin-on glass and oxide underlying the openings in the photoresist mask are partially etched; then the photoresist mask is removed; and blanket etchback of the spin-on glass and exposed oxide produces a relatively planar surface.
While these inventions result in improvements to the planarization processes they do not result in completely planar surfaces because of the implicit non-uniformities of the various process steps.
The present invention is directed to a novel and improved method for the formation of a planarized layer over topographic features on a semiconductor substrate. The novel and improved method compensates for non-uniformity of material removal during chemical/mechanical polishing (CMP) and results in a planarized layer having more uniform thickness.